1. Field of the Invention
The invention relates in general to a method for controlling read power and an open-loop read control device using the same, and more particularly to an open-loop read control device that generates a read power control voltage to control read power of a writing laser diode.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional CD writer. Referring to FIG. 1, the optical disk writer mainly has a read control device 10, a write control device 20 and a pickup head device 30. When the data read/write operation is to be performed, the driving circuit 304 of the pickup head device 30 generates a current iD flowing through a laser diode 301 so as to generate a laser beam to read/write a CD-R disk 40. The pickup head device 30 has a monitor diode 302 for generating a current iM according to the laser beam generated by the laser diode 301. An OP amplifier 303 processes the current iM and generates a feedback control signal FPDO. The feedback control signal FPDO is fed back to the input terminals of the read control device 10 and the write control device 20 in order to control read/write power of the laser diode 301 when the read/write operation is being performed. The current iD from the driving circuit 304 is controlled by signals from the read control device 10 and the write control device. The read control device 10 produces a read voltage VRDC which is transmitted through the resistor Rset1 to the driving circuit 304 and the write control device 20 produces a write voltage VWDC which is transmitted through the resistor Rset2 to the driving circuit 304.
FIG. 2 is a detailed circuit block diagram showing a read control device 10 and a write control device 20. As shown in FIG. 2, after the feedback control signal FPDO is inputted to the read control device 10, a sample/hold unit (S/H) 101 samples and holds the signal FPDO to obtain a signal FPDO_SH and input the signal FPDO_SH to a negative input terminal of an amplifier 102. A reference voltage Vref is inputted to a positive input terminal of the amplifier 102. An output signal dV1 of the amplifier 102 equals a difference between the signal FPDO_SH and the reference voltage Vref. The output signal dV1 is amplified by G11 times and then inputted to a negative input terminal of an amplifier (OP1) 103 through a resistor Ri1. A voltage DAC1 is inputted to a positive input terminal of the amplifier (OP1) 103. Consequently, a signal VRDCO outputted from the amplifier OP1 equals DAC1+(Rf1/Ri1)*(DAC1−(Vref−FPDO_SH)*G11).
FIG. 3 shows signal waveforms of the feedback control signal FPDO and a read sampling signal Rfpdo_SH when a low-speed write operation is being performed. In time slot T1, a potential difference between the feedback control signal FPDO and the reference signal Vref is ΔV1 , and the laser diode 301 outputs a light ray according to the stronger write power such that a pit is formed on the CD-R disk. In time slot T2, the potential difference between the feedback control signal FPDO and the reference signal Vref is ΔV2, which is smaller than ΔV1, the laser diode 301 outputs a light ray according to the weaker read power such that a land is formed on the CD-R disk.
When the read sampling signal Rfpdo_SH is high, the sample/hold unit S/H samples the feedback control signal FPDO to obtain the signal FPDO_SH. Usually, the read sampling signal Rfpdo_SH turns into high when the feedback control signal FPDO approaches the stable state in time slot T2.
FIG. 4 shows signal waveforms of the feedback control signal FPDO′ and the read sampling signal Rfpdo_SH′ when the high-speed write operation is being performed. As shown in FIG. 4, when the high-speed write operation is performed, the obtained feedback control signal FPDO′ becomes very unstable because the disk is rotated very fast and the laser diode has to output a stronger write power to write in time slot T1′. The unstable feedback control signal FPDO′ disables the sample/hold unit S/H from correctly sampling the feedback control signal FPDO′ in time slot T2′, and the feedback control signal obtained by the sample/hold unit (S/H) is usually too high. In this condition, the timing of the read sampling signal Rfpdo_SH′ usually has to be finely tuned, and the value of the voltage DAC1 is changed by way of try and error in order to improve the system's stability. However, such a way is very complicated and time-consuming. Thus, it is necessary to design an associated circuit to solve the above-mentioned problems.